In response to the American company, Rambus, developing their Next - Generation High - Speed Memory Interface Rambus DRAM (RDRAM(R) (*1)), Hitachi Cable, Ltd. developed tape for use in super compact semi-conductor packages & will start mass production. From this Fall we will start actual production and by around the end of next year expect to be set up to mass produce 50 million pieces per month.

By using the µBGA(R)(*2) semi conductor package technology, as developed by the American company Tessera as a base, we together with Hitachi Ltd. developed an improved tape and packages that use this tape can be ensured of higher reliability and more productivity compared to the former µBGA(R).

The main features of this package (*3), are as follows:
1. It achieves JEDEC Level 1(*4), so high package reliability can be ensured.
2. The production method is different from the package mold used to make existing Leadframes. A huge increase in productivity is made possible by using the Reel to Reel method whereby the chip is actually mounted on the long stretch of tape. Because of this, in the future we expect the price to be about the same as that of TSOP (Thin Small Outline Package).

When Rambus became aware of the superior electrical performance of µBGA(R), they decided to use it as the standard package for their Rambus DRAM as they highly value our technology. So, now we have begun to set up the early stages of a mass production system for this super compact semi-conductor package use tape.
When compared to the DRAM (memory capacity necessary for the exclusive use of entry & readout memory) which has been used up to now, the rapid speeds at which the Rambus DRAM can communicate data is one of the key features. This feature prompted the American company Intel, to use it for the main memory of their Next-Generation Personal Computer; it is expected that mass production will be started this Fall.

For Flash Memory, up to now we have been steadily achieving mass production of the tape & package structures. We have already started partly producing the tape for use in super compact semi-conductor packages & package mounting. As we expect that, in the high speed interface memory field, the Rambus DRAM package structure will rapidly become popular, we will try to make de facto standards on the package that use this tape, and along with the cooperation given by Hitachi Ltd. we forecast a monthly production amount of 10 million package structures in the early stages expecting capacity to increase in the future. At this time we forecast that the total sales amount for the tape & packaging will be in excess of 20 billion yen in 2000.

RDRAM(R) is a registered trademark of the American company, Rambus Inc.
µBGA(R) is a registered trademark of the American company, Tessera Inc.

Points of reference about Rambus Inc.

Rambus Inc. based in Mountain View, California, develops & licenses high-speed memory-interface technology. They have given widespread licenses, for their developed memory interface technology, to leading DRAM, ASIC & P.C. chip set manufacturers. Now, 8 of the top 10 global semi conductor manufacturers have acquired licenses for their technology, & the top 7 P.C. makers are manufacturing systems that use the same technology. For further details concerning Rambus Inc., please refer to their Internet

• http://www.rambus.com/ (English)
• http://www.rambus.co.jp (Japanese)

Supplementary notes

*1	RDRAM(R) (Rambus Dynamic Random Access Memory) - a registered trademark of the American company, Rambus Inc. When Intel Inc., one of the semi conductor maker giants, announced that they were going to use the High-Speed Memory Interface that Rambus Inc. had developed, in their main memory; the next generation DRAM trend was surely established. Up to now the fastest DRAM amongst the highest standard RDRAM(R) is the *Direct RDRAM(TM). The amount of data (peak band width) it can transmit in its unit speed CPU memory time is 1.6 GB/second which is realized in a single device. It is a DRAM device that extends over many generations it supports a capacity of up to 1 GB. Suitable areas of use for the RDRAM(R)include: Computer System Memory, Multi-Media Graphic Memory, Communication System Memory & Everyday use System Memory etc. *Direct RDRAM(TM) is a trademark of Rambus Inc.
*2	µBGA(R) ( a registered trademark of the American company, Tessera Inc.) Tessera Inc.hold a patent on the BGA type package. The structure of the so called BGA (Ball Grid Array) Package does not have the same leadframe pin arrangements, running along the outer edge, as the QFP (Quad Flat Package) structure which was used in the past. It has a uniform lattice arrangement of solder balls on it base, so it is able to answer the demands for a miniature package with a high pin count. Amongst a number of BGA the µBGA(R) holds the superior qualities of being highly reliable & able to realize high speed devices. We & Hitachi Ltd. have both acquired licenses for µBGA(R), from Tessera Inc.
*3	The difference between the µBGA(R) technology we have now developed & the technology we used in the past. With the µBGA(R) structure the chip is mounted on elastomar (a buffer material). Regarding the formation method of this elastomar, the previous µBGA(R) used the printing method, but the newly developed technology uses a method of sticking the elastic film material. The newly developed technology has measurement stability, can be mass produced & can greatly improve the process for products which involve attaching by soldering. As for the resin encapsulation method, before the Underfill method was used, whereby the chip surface & sides are filled up from the bottom up with resin, but the newly developed technology uses the Potting method where the resin is put on the chip surface & sides from the top. In the past the solder ball shapes of the µBGA(R) were formed by the Photo Resist method after encapsulation, but now with the tape shape process, they can be formed with a punching tool, so it has been possible to make the manufacturing process a lot simpler.
*4	JEDEC Level The JEDEC (Joint Electron Device Engineering Council), are a public body promoting the standardization of semi conductors, under the American EIA organisation. (Based in Arlington, Virginia) One of JEDEC's standardization items is the regulation of the quality of those packages used in semi conductor packages attached to print boards. On the surface mounted package, when the solder balls are being attached if moisture is present & the moisture is absorbed, there will be an explosion & the package will break. The levels are decided in order of durable superiority on this matter. Level 1 is the best quality, & shows a level where the semi conductor is definitely in a damp proof package. The technology used for the super compact semi-conductor package that we have illustrated this time is the first the world to attain level 1. JEDEC Level 1 - Outline Semi conductor preservation condition: 30 degree Centigrade, Less than 90% humidity - without restrictions. Trial conditions: 85 degree Centigrade, 85% humidity, 168 hours.